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Publications

B. Knerr, M. Holzer, C. Angerer, M. Rupp

Slot-Wise Maximum Likelihood Estimation of the Tag Population Size in FSA Protocols, IEEE Transactions on Communications, 58(2) , pages 578 - 585, 2010. [BibTeX]

M. Rupp, B. Knerr, M. Holzer

Heuristic Optimisation Methods for System Partitioning in HW/SW Co-Design, presented at Technische Universität Madrid, Madrid, October, 2008. (invited) [BibTeX]

M. Holzer, B. Knerr, C. Angerer, M. Rupp

Early Frame Restart in RFID Systems, in Proc. The Second International EURASIP Workshop on RFID Technology, Budapest, July, 2008. [BibTeX]

B. Knerr, M. Holzer, C. Angerer, M. Rupp

Slot-by-slot Minimum Squared Error Estimator for Tag Populations in FSA Protocols, in Proc. The 2nd Int. EURASIP Workshop on RFID Technology, pages 1 - 13, Budapest, July, 2008. [BibTeX]

B. Knerr, M. Holzer, C. Angerer, M. Rupp

Slot-by-slot Maximum Likelihood Estimation of Tag Populations in Framed Slotted Aloha Protocols, in Proc. 2008 Int. Symposium on Performance Evaluation of Computer and Telecommunication Systems, pages 303 - 308, Edinburgh, UK, June, 2008. [BibTeX]

C. Angerer, M. Holzer, B. Knerr, M. Rupp

A Flexible Dual Frequency Testbed for RFID, in Proc. Tridentcom08: proceedings of the 4th International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities, Innsbruck, March, 2008. [BibTeX]

M. Holzer

Design Space Exploration for the Development of Embedded Systems, PhD thesis, Institut für Nachrichten- und Hochfrequenztechnik, Vienna University of Technology, 2008. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

RRES: A Novel Approach to the Partitioning Problem for a Typical Subset of System Graphs, EURASIP Journal on Embedded Systems, 2008, pages 1 - 13, 2008. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Restricted Range Exhaustive Search: A New Heuristic for HW/SW Partitioning of Task Graphs, in Proc. Proceedings XXII Conference on Design of Circuits and Integrated Systems, pages 241 - 246, Sevilla, Spanien, November, 2007. [BibTeX]

M. Holzer, B. Knerr, M. Rupp

Design Space Exploration for Real-Time Reconfigurable Computing, in Proc. Asilomar Conference on Signals, Systems, and Computers, pages 1981 - 1985, Pacific Grove, CA, USA, November, 2007. (invited) [BibTeX]

C. Angerer, M. Holzer

Flexible Simulation and Prototyping for RFID Designs, presented at ftw RFID Tutorial, Wien, October, 2007. (invited) [BibTeX]

C. Angerer, B. Knerr, M. Holzer, A. Adalan, M. Rupp

Flexible Simulation and Prototyping for RFID Designs, in Proc. The first international EURASIP Workshop on RFID Technology, RFID 2007, Book of Proceedings, pages 51 - 54, Wien, September, 2007. [BibTeX]

M. Holzer, B. Knerr, M. Rupp

Design Space Exploration with Evolutionary Multi-Objective Optimisation, in Proc. 2007 Symposium on Industrial Embedded Systems Proceedings, pages 126 - 133, Lisbon, Portugal, July, 2007. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Novel Genome Coding of Genetic Algorithms for the System Partitioning Problem, in Proc. 2007 Symposium on Industrial Embedded Systems Proceedings, pages 134 - 141, Lissabon, Portugal, July, 2007. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Improvements Of The Gclp Algorithm For Hw/sw Partitioning Of Task Graphs, in Proc. Proceedings of the 4th IASTED International Conference on Circuits, Systems, and Signals, pages 107 - 113, San Francisco, CA, USA, November, 2006. [BibTeX]

M. Holzer, B. Knerr, M. Rupp

Structural Verification in Minimal Time, in Proc. International Symposium on System-on-Chip, pages 151 - 154, Tampere, Finnland, November, 2006. [BibTeX]

M. Holzer, B. Knerr

Pareto Front Generation for a Tradeoff between Area and Timing, in Proc. Austrochip 2006 Tagungsband, pages 131 - 134, Messegelände Wien, Österreich, October, 2006. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Extending the GCLP Algorithm for HW/SW Partitioning: A Detailed Platform Model and Performance Improvements, in Proc. Austrochip 2006 Tagungsband, pages 89 - 95, Messezentrum Wien, Österreich, October, 2006. [BibTeX]

M. Holzer, M. Rupp

Static Code Analysis of Functional Descriptions in SystemC, in Proc. DELTA 2006 Third IEEE International Workshop on Electronic Design, Test & Applications, pages 243 - 248, Kuala Lumpur, Malaysia, January, 2006. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

A Fast Rescheduling Heuristic of SDF Graphs for HW/SW Partitioning Algorithms, in Proc. Proceedings of COMSWARE 2006, New Delhi, India, January, 2006. [BibTeX]

M. Holzer, B. Knerr, P. Belanovic, M. Rupp

Efficient Design Methods for Embedded Communication Systems, EURASIP Journal on Embedded Systems(ID 64913) , 2006. [BibTeX]

P. Belanovic, B. Knerr, M. Holzer, M. Rupp

A Fully Automated Environment for Verification of Virtual Prototypes, EURASIP Journal on Applied Signal Processing, 2006, pages 1 - 12, 2006. [BibTeX]

P. Belanovic, M. Holzer, B. Knerr, M. Rupp

Automated Verification Pattern Refinement for Virtual Prototypes, in Proc. Conference of Design of Circuits and Integrated Systems, Lissabon, Portugal, November, 2005. [BibTeX]

M. Holzer, M. Rupp

Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips, in Proc. Proceedings of International Symposium on System-on-Chip 2005, pages 62 - 65, Tampere, Finland, November, 2005. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms, in Proc. Proceedings of Thirty-Ninth Annual Asilomar Conference on Signals, Systems, and Computers, pages 1375 - 1379, Pacific Grove, CA, USA, October, 2005. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs, in Proc. Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design, pages 50 - 55, Florianapolis, Brazil, September, 2005. [BibTeX]

M. Holzer, P. Belanovic, B. Knerr, M. Rupp

Automatic Design Techniques for Embedded Systems, in Proc. Proceedings of GI/ITG/GMM Workshop Modellierung und Verifikation, Munich, Germany, April, 2005. [BibTeX]

P. Belanovic, B. Knerr, M. Holzer, G. Sauzon, M. Rupp

A Consistent Design Methodology for Wireless Embedded Systems, EURASIP Journal on Applied Signal Processing, Vol. 2005(16) , pages 2598 - 2612, 2005. [BibTeX]

B. Knerr, P. Belanovic, M. Holzer, G. Sauzon, M. Rupp

Design Flow Improvements for Embedded Wireless Receivers, in Proc. EUSIPCO 2004 12th European Signal Processing Conference, pages 2015 - 2018, Wien, September, 2004. [BibTeX]

B. Knerr, M. Holzer, M. Rupp

HW/SW Partitioning Using High Level Metrics, in Proc. Proceedings of the International Conference on Computing, Communications and Control Technologies, pages 33 - 38, Austin, Texas, August, 2004. (invited) [BibTeX]

B. Knerr, M. Holzer, P. Belanovic, G. Sauzon, M. Rupp

Advanced UMTS Receiver Chip Design Using Virtual Prototyping, in Proc. Proceedings of the 2004 International Symposium on Signals, Systems and Electronics ISSSE 04, Linz, Österreich, August, 2004. [BibTeX]

M. Holzer, B. Knerr, P. Belanovic, M. Rupp, G. Sauzon

Faster Complex SoC Design by Virtual Prototyping, in Proc. Proceedings of CITSA Internattional Conference on Cybernetics and Information Technologies, Systems and Applications, pages 305 - 309, Orlando, Florida, July, 2004. [BibTeX]

P. Belanovic, M. Holzer, B. Knerr, M. Rupp, G. Sauzon

Automatic Generation of Virtual Prototypes, in Proc. Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping RSP 04, pages 114 - 118, Genf, Schweiz, June, 2004. [BibTeX]

M. Holzer, P. Belanovic, B. Knerr, M. Rupp

Design Methodology for Signal Processing in Wireless Systems, in Proc. Informationstagung Mikroelektronik, pages 303 - 307, Vienna, October, 2003. [BibTeX]

P. Belanovic, M. Holzer, D. Micusik, M. Rupp

Design Methodology of Signal Processing Algorithms in Wireless Systems, in Proc. International Conference on Computer, Communication and Control Technologies: CCCT 03, pages 288 - 291, Orlando, USA, July, 2003. [BibTeX]

M. Holzer, P. Belanovic, M. Rupp

A Consistent Design Methodology to Meet SDR Challenges, in Proc. 9th Wireless World Research Forum Meeting, Zürich, July, 2003. [BibTeX]

B. Grankl, M. Holzer, P. Rössler

Entwicklung eines skalierbaren Z80-Prozessormodells, in Proc. Tagungsband zur Austrochip ´99, pages 77 - 82, Villach, September, 1999. [BibTeX]

M. Holzer

VHDL-Modell einer Scalable Processing Unit (SPU), Master's thesis, E 384, Vienna University of Technology, 1999. [BibTeX]

Go to: Martin HOLZER Martin HOLZER - Publications