UNFOLD

Unleashing Finite-Alphabet Implementations of LDPC Decoders

 —-   —-   —-

 

 

 



Chip layout for a 588Gbps LDPC decoder designed for 10GBASE-T Ethernet using the UNFOLD software framework (see reference [4] below for details).

AIM

Since there exists no perfect medium for transmitting or storing digital information, every communication system is bound to suffer from errors. These errors are combated by means of error-correcting codes. Because of their outstanding performance, low-density parity check (LDPC) codes are used in many applications (e.g., digital television, cellular, WLAN, Ethernet, hard drives and flash memory) and are therefore of great practical importance. One of the biggest technological challenges with LDPC codes is the hardware implementation of the associated decoders. Many companies and research institutes are working to develop efficient integrated circuits for LDPC codes that enable rapid and power-efficient error correction with a small chip area. The aim of the UNFOLD project was to evolve the latest results from our research into a full-fledged software development environment for the design, implementation, and testing of LDPC decoders. More specifically, the UNFOLD project contributes to realizing the full practical potential of finite-alphabet/lookup-table decoders for LDPC codes. This decoder type is a recent innovation, for which theoretical foundations and preliminary hardware architecture aspects have been investigated in the context of our previous WWTF project TINCOIN. UNFOLD takes a leap forward to the next application level by providing a development and design flow for finite-alphabet LDPC decoders in the form of a software suite and soft-IP cores. These tools enable manufacturers to implement LDPC decoders of unprecedented hardware performance in semiconductor chips with short development times. The chips thus realized are potentially much smaller and cheaper than currently existing hardware, and accordingly can lead to a substantial competitive advantage.

The UNFOLD project is funded by the WWTF within the NEXT Call (WWTF Grant NXT17-013).


TEAM

The UNFOLD project is a collaboration of the Communication Theory Group at the Institute of Telecommunications of TU Wien and the Telecommunications Circuits Laboratory at Ecole Polytechnique Fédérale de Lausanne (EPFL). Key team members are Prof. Gerald Matz, Prof. Andy Burg, Dr. Michael Meidlinger, Dr. Alexios Balatsoukas Stimming,  and Reza Ghanaatian Jahromi.


SOFTWARE FRAMEWORK

In the context of UNFOLD, we developed a C++/Matlab software suite that covers the complete design flow for finite alphabet/lookup table (LUT) decoders of LDPC codes, i.e., the conception and implementation of lookup table trees, unrolled decoders with LUT reuse, VHDL code generation, density evolution for LUT decoding, and Monte Carlo error rate simulations. A more detailed documentation can be found here.

LUT-LDPC

LUT-LDPC is a C++ program / library that can be used for the design and performance evaluation of LUT-based discrete message passing LDPC decoders. Decoders can be designed and tested for their error rate performance as well as exported to produce VHDL implementations of unrolled decoders.

Github download link: LUT-LDPC

Documentation and how-to-use guide: LUT-LDPC documentation

LUT-LDPC-VHDL

LUT-LDPC-VHDL is a collection of MATLAB sctipts that takes a decoder object generated with the LUT-LDPC C++ program as an input and produces VHDL source code for this decoder assuming an unrolled architecture.

Github download link (includes documentation): LUT-LDPC-VHDL

Example Design Flow
Decoder design flow

Assuming you have installed LUT-LDPC, the following command runs LUT-LDPC and produces a decoder object and corresponding test vectors for VHDL verification:

ber/sim -p params/ber.ini.regular.example > stimuli.txt

The resulting decoder object lut_codec.it can then be used to produce the corresponding VHDL source of an unrolled decoder using the LUT-LDPC-VHDL MATLAB script decoderGenerator.m.

The functionality of the resulting VHDL code can be verified against the functionality of the LUT-LDPC software decoders using the test vectors and the accompanying ModelSim Testbench.

Click here for a more detailed documentation.